The W5500 chip is a Hardwired TCP/IP embedded Ethernet controller that enables easier internet connection for embedded systems using SPI (Serial Peripheral Interface).
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|Embedded Core||TCP/IP, MAC & PHY|
|Host Interface||Fast SPI|
|Number of Hardware Socket||8|
|Network Performance||Max 15Mbps|
|Operation Temp (℃)||-40 ~ 85|
|Package Type||48LQFP (7x7)|
The W5500 chip is a Hardwired TCP/IP embedded Ethernet controller that enables easier internet connection for embedded systems using SPI (Serial Peripheral Interface). W5500 suits users in need of stable internet connectivity best, using a single chip to implement TCP/IP Stack, 10/100 Ethernet MAC and PHY. Hardwired TCP/IP stack supports TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE, …, which has been proven through various applications over many years. W5500 uses a 32Kbytes internal buffer as its data communication memory. By using W5500, users can implement the Ethernet application they need by using a simple socket program instead of handling a complex Ethernet Controller. It is possible to use 8 independent hardware sockets simultaneously. SPI (Serial Peripheral Interface) is provided for easy integration with the external MCU. The W5500 SPI supports 80 MHz speed …and the new efficient SPI protocol, so users can implement high speed network communication. In order to reduce power consumption of the system, W5500 provides WOL (Wake on LAN) and a power down mode.
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