W7500P

New product

The IOP (Internet Offload Processor) W7500P  is the one-chip solution which integrates an ARM Cortex-M0, 128KB Flash and hardwired TCP/IP core & PHY for various embedded application platform especially requiring ‘Internet of things’.

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HKD26.00

The minimum purchase order quantity for the product is 5

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Data sheet

Embedded CoreCortex-M0, TCP/IP, MAC & PHY
TX/RX Buffer32KB
Number of Hardware Socket8
Operation Temp (℃)-40 ~ 85
Process0.13µm
Package Type64 TQFP (7x7)

More info

The TCP/IP core is a market-proven hardwired TCP/IP stack with an integrated Ethernet MAC. The Hardwired TCP/IP stack supports the TCP, UDP, IPv4, ICMP, ARP, IGMP and PPPoE which has been used in various applications for years. W7500P suits best for users who need Internet connectivity for application.

Key Features

ARM Cortex-M0

  • 48MHz maximum frequency

Hardwired TCP/IP Core

  • 8 Sockets

  • SRAM for socket: Max. 32KB

  • MII (Medium-Independent Interface)

PHY

  • IC Plus (IP101G)

Memories

  • Flash: 128 KB

  • SRAM: 16KB to 48 KB ( Min 16KB available if 32KB socket buffer is used, Max 48KB available if no socket buffer is used)

  • ROM for boot code: 6KB

Clock, reset and supply management

  • POR (Power-On Reset)

  • Internal Voltage Regulator : 3.3V to 1.5V

  • 8-to-24MHz external crystal oscillator

  • Internal 8MHz RC Oscillator

  • PLL for CPU clock

ADC

  •  12bit, 8ch, 1Msps

DMA

  • 6-channel DMA controller

  • Peripheral supported: UARTs, SPIs

GPIO

  • 34 I/Os (15 IO x 2ea, 4 IO x 1ea)

Debug mode

  • Serial Wire Debug (SWD)

Timer/PWM

  • 1 Watchdog (32-bit down-counter)

  • 4 Timers (32-bit or 16-bit down-counter)

  • 8 PWMs (32-bit counter/timers with programmable 6-bit prescaler)

Communication Interfaces

  • 3 UART (2 UARTs with FIFO and Flow Control, 1 simple UART)

  • 2 SPI

  • 2 I2C (Master/Slave, Fast-mode (400 kbps))

Crypto

  • 1 RNG (Random Number Generator): 32-bit random number

Package

  • 64 TQFP (7×7 mm)

Block Diagram

Download

Documents

Documents W7500P Datasheet  

  • You can download the latest version of W7500 Datasheet

W7500 Reference Manual 

  • You can download the latest version of W7500 Reference Manual

W7500 Application Note

  • How to install KEIL
  • How to make KEIL new project for W7500P
  • How to use MDK for W7500P Peripheral Examples
  • How to use GCC for W7500 Peripheral Examples

Library & Peripheral Examples

Library W7500 Library & Peripheral Example

The W7500 provides the CMSIS driver and Peripheral example. The W7500 Standard Peripherals library provides a rich set of examples covering the main features of each peripheral. Only source files are provided for each example and user can tailor the provided project template to run the selected example with his preferred tool-chain.

Hardware Design Guide

Hardware Materials WIZwiki-W7500 Schematic

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W7500P

W7500P

The IOP (Internet Offload Processor) W7500P  is the one-chip solution which integrates an ARM Cortex-M0, 128KB Flash and hardwired TCP/IP core & PHY for various embedded application platform especially requiring ‘Internet of things’.

Download

w7500p_ds_v104.pdf

W7500P Datasheet v1.0.4 - English

Download (1.44M)

w7500_reset_pin_design_guide_eng

IOP4IoT W7500/ W7500P Schematic Design Guide

Download (174.7k)

w7500_ref_schematic_v1.1_ip.pdf

W7500 Reference Schematic with IP101GA

Download (418.81k)

w7500_ref_schematic_v1.1_rtl.pdf

W7500 Reference Schematic with RTL8201CP-VD-LF

Download (445.53k)