W5100S

New product

Hardwired TCP/IP w/ 802.3 Ethernet MAC and PHY, 4-sockets, Fast SPI/BUS

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In stock

HKD20.20

  • 48LQFP
  • 48QFN

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QuantityPriceYou Save
250 HKD16.30 Up to HKD975.00
2500 HKD13.20 Up to HKD17,500.00

Data sheet

Embedded CoreTCP/IP, MAC & PHY
Host Interface8bit BUS, SPI
TX/RX Buffer16KB
Number of Hardware Socket4
Network PerformanceMax 25Mbps
Operation Temp (℃)-40 ~ 85
Package Type48LQFP / QFN (7x7)

More info

W5100S is an embedded Ethernet controller designed as a full hardwired TCP / IP with WIZnet technology. W5100S provides internet connectivity to your embedded system by using SPI (Serial Peripheral Interface) or Parallel System BUS.

SPI and Parallel System BUS provide easy connection via external MCU to W5100S.The clock speed of W5100S SPI supports upto 70MHz and the Parallel System Bus supports higher speed network communication than SPI.

Since W5100S integrates the Hardwired TCP/IP stack with 10/100 Ethernet MAC and PHY, it is truly a one-chip solution for the stable internet connectivity.

WIZnet’s hardwired TCP/IP stack supports TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE – and it has been proven through various applications over the last decade.

W5100S provides four independent SOCKETs to be used simultaneously and 16KB internal memory for data communication.

Users can develop an Ethernet application easily by using the simple W5100S SOCKET program instead of handling a complex Ethernet controller.

W5100S also provides WOL (Wake on LAN) and a Power Down Mode in order to reduce power consumption.

W5100S is a low-cost chip that exceeds its predecessor, W5100.Existing firmware using W5100 can be used on W5100S without modification.W5100S has two types of packages, 48 Pin LQFP & QFN Lead-Free Package.

Features

  • Support Hardwired Internet protocols : TCP, UDP, WOL over UDP, ICMP, IGMPv1/v2, IPv4, ARP, PPPoE
  • Support 4 independent SOCKETs simultaneously
  • Support SOCKET-less command : ARP-Request, PING-Request
  • Support Ethernet Power Down Mode & Main Clock gating for power save
  • Support Wake on LAN over UDP
  • Support Serial & Parallel Host Interface : High Speed SPI(MODE 0/3), Parallel System Bus with 2 Address signal & 8bit Data
  • Internal 16Kbytes Memory for TX/ RX Buffer
  • 10BaseT/100BaseTX Ethernet PHY Integrated
  • Support Auto Negotiation (Full Half Duplex, 10 100-based )
  • Support Auto-MDIX only when Auto-Negotiation mode
  • 3V operation with 5V I/O signal tolerance
  • Network Indicator LEDs (Full/Half Duplex, Link, 10/100 Speed, Active)
  • 48 Pin LQFP & QFN Lead-Free Package (7x7mm, 0.5mm pitch)

Block Diagram

Pin Assignment


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W5100S

W5100S

Hardwired TCP/IP w/ 802.3 Ethernet MAC and PHY, 4-sockets, Fast SPI/BUS